SAN JOSE, Calif.--(BUSINESS WIRE)--

Advanced Chip and Circuit Materials today announces the commercial availability of Celeritas HM50 and Celeritas HM001, which eliminate the root causes of warpage, package bow, solder fatigue, and high-frequency signal loss in large-format AI accelerators and advanced chip packaging architectures. Celeritas HM50 is a negative CTE (-8 PPM/°C) material and Celeritas HM001 is a near-zero CTE material. Used together in a single stackup, they bring board CTE below 10 ppm/°C while simultaneously delivering Tier 9 electrical performance.

This press release features multimedia. View the full release here: https://www.businesswire.com/news/home/20260414615509/en/

Every hyperscaler building AI infrastructure is confronting the same pair of converging constraints. As AI accelerators scale beyond reticle limits, thermomechanical mismatch between silicon (2–4 ppm/°C) and standard PCB materials (~18 ppm/°C) produces catastrophic reflow warpage, package bow, and solder joint fatigue. Simultaneously, the explosive growth in data rates, driven by HBM, UCIe, and chip-to-chip interconnect operating at 100+ Gbps, is pushing signal integrity requirements beyond what standard PCB dielectrics can support. The industry has been searching for two separate solutions to two separate problems. ACCM has built one material family that addresses both.

The industry's leading proposed fix of solid glass substrates remains positive in CTE and does not address the electrical side at all. ACCM today announced Celeritas HM50 and Celeritas HM001, which together solve both problems simultaneously. Programs can start today.

“Rather than incrementally tuning stackups, we are applying a breakthrough materials innovation to remove a fundamental limitation that has constrained system scaling. HM50, with its negative CTE of -8 PPM/°C, drives the effective CTE of the board down. Even with heavy copper designs, you could tune a board down to 12, 10, 8 PPM/°C or lower. And where next-generation data rates demand extreme loss performance, HM001 replaces those layers with a Tier 9 loss material that has a near-zero CTE. Together, they give designers headroom they simply have not had before.”

— Keshav Amla, COO, Advanced Chip & Circuit Materials

The HM Class of materials matches each layer type in an AI accelerator stackup with a material purpose-built for it: HM50 for the power planes, HM001 for the signal layers.

Celeritas HM50

Celeritas HM50 has a CTE of −8 ppm/°C – the material itself is negative. Mixed into a standard stackup at the power plane layers, it drives the effective board CTE continuously downward, enabling effective CTE tuning of a board. The FEA results quantify what that means in practice: 64% warpage reduction, 81% package bow reduction, and >100× solder fatigue life improvement versus standard high-speed materials – taking a design that fails JEDEC qualification outright to one that exceeds it by orders of magnitude. With Dk 3.55 and Df 0.0055, HM50 is also, from an electrical standpoint, a Tier 6 material, a major step up from standard FR4 in its own right. This product is ready for production.

Celeritas HM001

Celeritas HM001 replaces conventional high-speed dielectrics in signal layers. At